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I would like to thank you all for the kind wishes to my birthday on Saturday. As i'm present on several social networks, i virtually got wishes to each of them ... so i thought i just "consolidate" my thankyou here

Oracle VM for SPARC 2.2 (the product formerly known as Logical Domains) was released today. There are a some important changes in this new release:

• Support for PCIe Single Root I/O Virtualization (SR-IOV) physical functions and virtual functions. Raghuram Kothakota's blog entry
• Support for performing named CPU core and memory block assignments.
• CPU whole-core allocation enhancement.
• Cross-CPU migration support. Jeff Savit wrote a great article to explain this feature. You can now live migrate to a different type of sun4v CPU. Before 2.2. you could just migrate to exactly the same type of processor.
• Virtual I/O support for Rx Dring mode.
• Bug fixes

You will find the release notes here.

Sometimes it's quite handy to have a good explanation, why distance equals time, and why this is important in computing. RDML Hopper finds a 30 cm cable quite useful in order to explain that. Thanks to Youtube i find it really useful that there is now the opportunity to let her tell this for herself. Perhaps it would be really quite useful to have some nanoseconds on your desk. Or threehundred metres Cat7 to demonstrate a microsecond.

I really like to read our internal aliases. Because sometimes you are stumbling about a piece of information that reminds you that it could be a article for the blog. In this case it was about the topic of the virtual memory translation. I will simplyfing things a bit, so dear experts, i know that the situation is more complex For people interested in more details the chapters 9-12 and chapter 3 Section 3.11.7 of "Solaris Internals: Solaris 10 and OpenSolaris Kernel Architecture (2nd Edition): Solaris 10 and Open Solaris Kernel Architecture" is a good start.

Whenever you use some virtual memory, there has to be some mapping from the virtual addresses to the real addresses. However to prevent the CPU to look again and again in - from CPU cycles perpective - distant memory areas, there are little caches in modern processors called translation lookaside buffer or short TLB. This TLBs are rather small, a T4 core has 128 entries. While sounding small, the TLB with such a number of entries has an astonishing high hit rate.