Quicksearch
Disclaimer
The individual owning this blog works for Oracle in Germany. The opinions expressed here are his own, are not necessarily reviewed in advance by anyone but the individual author, and neither Oracle nor any other party necessarily agrees with them.
New Power6 systems
Wednesday, January 30. 2008
IBM announced new Power6 based systems today. The p520 Express and the p550 Express. This announcement is somewhat hidden in the PowerVM announcement.Well, now legions of IBM sales reps will go to customers and tell them: "We have Power6 in smaller systems. Not only in p570". But you have to take this comment with a really large amount of salt.
When you look into the data sheets you find some interesting facts. You won´t get 4.7 Ghz p6 with the new systems. The p520 is a 4.2 Ghz only system and the p550 is only available with 3.5 or 4.2 Ghz. So still no mass-rollout of the 4.7 GHz p6 silicon. IBM must still have yield problems with the high-end version.
More interesting is the fact, that the p520 doesn´t have the 32 MB L3 Cache of the larger boxes. I wrote about the effect of having less cache on the Power6 chip some weeks ago when the new blade was announced. Like with the blade: You get the p6 proc but not the p6 performance.
When you look into the data sheets you find some interesting facts. You won´t get 4.7 Ghz p6 with the new systems. The p520 is a 4.2 Ghz only system and the p550 is only available with 3.5 or 4.2 Ghz. So still no mass-rollout of the 4.7 GHz p6 silicon. IBM must still have yield problems with the high-end version.
More interesting is the fact, that the p520 doesn´t have the 32 MB L3 Cache of the larger boxes. I wrote about the effect of having less cache on the Power6 chip some weeks ago when the new blade was announced. Like with the blade: You get the p6 proc but not the p6 performance.
Trackbacks
Trackback specific URI for this entry
No Trackbacks
Comments
Display comments as
(Linear | Threaded)
Maybe it's not very unreasonable that the lower clock speed as well as the smaller third level cache is due to marketing reasons; IBM might want to get rid of Power5(+) rather sooner than later, thusly creating a Power6 CPU that is more or less equal on performance.
+1
The LKSF book
The book with the consolidated Less known Solaris Tutorials is available for download here
Web 2.0
Contact
Networking
xing.com
LinkedIn
Facebook
My photos
- mail: joerg@c0t0d0s0.org
- icq: 144000169
- Me, myself and I
- openBC
- My del.icio.us
- c0t0d0s0@twitter
- c0t0d0s0@last.fm
- wiki@c0t0d0s0
- Amazon Wishlist
Networking
xing.com
My photos
Comments
about Nanosecond
Wed, 23.05.2012 00:11
I remember this being drummed
into us during Digital Design
at Uni. It's important to cons
ider it when laying out [...]
Mon, 21.05.2012 18:04
Hello Kevin, Im not surprised
with what you are seeing or ha
ve seen when attaching a SSD t
o a USB2.0. USB3.0 helps [...]
Mon, 21.05.2012 04:44
Hi Greg,
With regards to IO
PS I have seen terrible result
s using a 60GB SATA2 SSD with
USB2.0 - USB2 really cho [...]
about ZFS Dedup Internals
Sat, 19.05.2012 09:50
There is no impact to boot/imp
ort times, as the DDT is loade
d as needed ... so the pool is
imported as fast as wit [...]
Buttons
This work is licensed under a Creative Commons Attribution-Noncommercial-Share Alike 3.0 Germany License
